1. Field of the Invention
The present invention relates generally to devices which share the use of a communication bus or the like, and, more particularly, to a circuit for forcing the device currently controlling the communication bus to relinquish control thereof and to retry the interrupted operation at a later time.
2. Background Art
In simple data processing systems, the central processing unit communicates directly with each of the peripherals and memory circuits via direct, dedicated communication lines. In more sophisticated data processing systems, a communication bus is used to couple the central processing unit to one or more memory units, peripheral controllers, channel controllers, and the like. In some of the systems, devices other than the central processing unit are allowed to request and receive temporary control of the communication bus from the central processing unit. Typically, these "bus masters" utilize the communication bus to rapidly perform their assigned tasks, and then return control of the communication bus to the central processing unit. However, the integrity of the system can be seriously compromised if a bus master assigned a time critical task is forced to wait until the bus master currently using the bus has completed the current operation.
In the past, some systems have limited the ability of each bus master to monopolize the communication bus by allowing only a single operation to be performed during each bus grant. This single transfer technique is generally impractical in systems which incorporate the newer forms of intelligent peripheral controllers, disc controllers, and the like, which are most effective for performing burst type transfers. In the latter type of system, the system software is typically designed to restrict the size of those operations which must be performed by the bus master during a single burst of activity on the communication bus. This software limitation technique imposes substantial overhead on the system, and still does not solve the dilemma of timely servicing of time critical tasks which become active while another bus master has control of the bus.